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MLC3500 is a single chip of multi
format digital audio decoder for
flash type MP3, WMA decoder with
a powerful RISC DSP controller
is embedded for high quality decoding
function. High quality voice encoding
and decoding function for low
bit rate (6.5Kbps) is supported
by MLCELP(MCS Logic proprietary
modified ADPCM) algorithm. |
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·
Single-chip MPEG 1/2 layer 2 and
3, WMA, ASF decoder
· Low bit rate MLCELP (MCS Logic
proprietary speech coding algorithm)
6.5Kbps
compression rate (fs=8KHz)
VAD(Voice
Activity Detection) / CNG(Comfort
Noise Generation) function
VOR(Voice
Operation Recording) function
· High quality MLPCM (MCS Logic
proprietary modified ADPCM algorithm)
32Kbps/64Kbps/128Kbps
compression rate (Fs=8KHz, 16KHz,
32KHz) |
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Physical
Features
· Supply Voltage : 2.5Vㅋ 10%,
I/O Supply Voltage : 3.3V 10%
· Input crystal frequency : 16.9344MHz
· Package type : 64-TQFP-1010
Firmware Features
· Support ID3 tag V1 and V2 extraction
· Extension to MPEG 2 / layer
3 for low bit rates (MPEG 2.5
- LSF)
· Bit streams with variable bit
rates (bit rate switching) are
supported
· Full bit rates MPEG file Decoding
including free format
· Full bit rates WMA file Decoding
· Support Digital volume control
· 7 band sound Equalizer for MP3
and WMA
· 7 band graphic Equalizer for
MP3 and WMA
· MEBB (MCS Logic Enhanced Bass
band) sound algorithm
· Optional sampling rate conversion
to 44.1Khz for off-chip general
audio DAC
· Channel mixing or separating
for two different audio sources
· Supports Software MUTE / Pause
/ Resume
· Supports total(only WMA file)
and play time display
· Support Digital volume control
for both encoding(recording) and
decoding(play)
· 7 steps playback speed control
· Channel mixing or separating
for two different voice sources
for both encode and decode
· Support encoding(recording)
and decoding(play) time display
External Audio CODEC Interface
· Standard serial PCM and I2S
mode supported
· Master mode only (AC_MCK, AC_BCK,
AC_LRCK pins are all output mode)
· ADC data input from external
CODEC is received via AC_DI pin
(encoding)
· DAC data output to external
CODEC is transmitted via AC_DO
pin (decoding)
· Support industry standard over-sampling
rates of 384Fs only
· Data transfer lengths of 16,
24, 32 bits per channel are supported
· LRCK, BCK polarity selectable
· Left/Right justified data align,
MSB/LSB first selectable
Host Interface
· Serial Interface : 4-wired data
interface ( SCLK, SDAT, SLAT,
SENSEB )
· Parallel Interface : 12-wired
data interface ( HAD[7:0], CSB(SDAT),
ALE(SCLK), RWB(SLAT), WAITB(SENSEB)
)
· Serial/Parallel host interface
is selectable by setting the HIMODE
pin
Bit Stream and Coded Voice Date
Port
· 3-wired serial bit stream and
coded voice data input/output
(SPI)
DREQB(O),
S_CLK(I), S_DI(I), S_DO(O)
· Parallel handshake bit stream
and coded voice data input/output
DIO[7:0]
bus is output mode with DREQB(O),
ILATB(I), OLATB(O) @encode, transmit
DIO[7:0]
bus is input mode with DREQB(O),
ILATB(I), OLATB(O)@decode, receive
· Serial/Parallel data interface
is selectable by setting the DIMODE
pin
· HAD[7:0] and DIO[7:0] bus can
be connected to same 8-bit data
bus of host controller to reduce
the number of pins
Five GPIO with 16-bit Timer
· General purpose I/O : 5-port
(GPIO4, GPIO3, GPIO2, GPIO1, GPIO0)
Host
controller can controls(data read
and write) these 5 GPIO independently
with host command
Alternative
16-bit timer related signals are
sharing these pins. GPIO0(TCAP/TOUT),
GPIO4(TCLK)
· 16-bit Timer
Three
operating mode
Match
mode with TOUT pin signal output
Capture
mode(falling or rising edge of
TCAP pin) with TDATA1,0 register
read by host controller
PWM
mode with TOUT pin signal output
Internal
and External Timer clock selectable
Internal
: 16.9344MHz, External : TCLK
pin input |
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