The MLC3700 is designed as a System On a Chip: system controller and decoder controller for multi-format digital audio player with access of various storage such as USB, SD/MMC card, NAND flash, Nor flash and etc. The 32-bit RISC processor provides optimum performance and code density for the combination of control code and signal processing required for digital audio decoding, file system management and system control.

The MLC3700 integrates programmable and approved ARM926EJ-S™ core for a system controller, multi-format digital audio (MP3/WMA/Ogg/AAC-LC/AAC+/MUSICAM/BSAC) decoding, On-chip SRAM and ROM, versatile audio interfaces of USB OTG, SD/MMC card, and NAND flash and large number of GPIOs (General Purpose Input Output) ports. In addition, SRS (WOW), MP3 encoding and WMA encoding features are available as system solutions. By utilizing advanced 0.13 micron technology, the MLC3700 is the perfect solution for digital audio products with low power consumption requirements; high performance and powerful processing .

1.2.1 PROCESS
 Low power 0.13 um CMOS technology
 Core Supply power: 1.12 V ∼ 1.28 V
 IO supply power : 3.3 V ± 10%

1.2.2 ARCHITECTURE
 SoC(System on Chip) for multi-format digital audio player
 32 bit RISC architecture and powerful instruction set with ARM926EJ-S™ CPU core
 4-way set-associative cache with I-Cache(8-Kbyte) and D-Cache(8-Kbyte)
 Internal AMBA™ (Advanced Microcontroller Bus Architecture(Rev2.0, AHB/APB)
1.2.3 PACKAGE TYPE
 208-LQFP-2828 (MLC3700C)
 176-LQFP-2020 E-PAD (MLC3700A)
 176-LQFP-2020 E-PAD (MLC3700B)
1.2.4 MEMORY
 4-Kbyte On-chip general purpose Data SRAM
 Max. 512-Mbit *2 SDRAM interface with 16-bit data width
1.2.5 GENERAL PURPOSE DMA
 Three channel general purpose DMA control block
1.2.6 USB- OTG CONTROLLER
 Compiles with the On-The-Go Supplement to the USB2.0 Specification(Revision 1.0a)
 Operates in High-Speed(HS,480-Mbps), Full-Speed(FS,12-Mbps) and Low-Speed(LS,1.5-Mbps) modes
 Support the UTMI+ Level3 interface(Revision 1.0, Feburary 25th,2004).8-,16- and 8/16-bit data buses are supported
 Supports ULPI interface(Revision 1.1rc,September 1st,2004) -8-bit SDR,4-bit DDR,6-pin Serial,3-Pin Serial and Carkit
 IF HSIC is selected, only UTMI+ L3 is supported and there is no ULPI support
 Supports Session Request Protocol(SRP)
 Supports Host Negotiation Protocol(HNP)
 I2C interface (for support of Mini USB Analog Carkit Interface Specification, CEA-936,Revision 2, not intended for use with other devices)
 Supports up to 16 bidirectional endpoints, including control endpoint 0
 Supports up to 16 host channels. In Host mode, when the number of device endpoints to be supported is more than the number of host channels, software can reprogram the channels to support up to 127 devices, each having 32 endpoints(IN+OUT), for a maximum of 4064 endpoints
 Supports a generic root hub
 Includes automatic ping capabilities
1.2.7 NAND FLASH CONTROLLER
 NAND type FLASH memory controller
- BCH codec: Max 14bits / 512Bytes correction ECC or
- BCH codec: Max 42bits / 1024Bytes correction ECC
 Support Dedicated DMA controller
 NAND Flash boot loader
1.2.8 SERIAL AUDIO DATA INTERFACE
 Two Channel I2S Mater / 5-wired interface (AMCLK, ALRCK, ABCLK, ADIO, ADI)
1.2.9 CDROM DECODER
 ISO9660 CDROM Mode1, Mode2 form1 & form2 Format decoding
1.2.10 SPDIF TRANSCEIVER
 IEC-958(SPDIF) compliant digital audio output
1.2.11 ETHERNET CONTROLLER
 DMA engine with burst mode
 DMA Tx/Rx buffers
 MAC Tx/Rx FIFO buffers
 Data alignment logic
 Endian translation
 100/10-Mbit per second operation
 Full compliance with IEEE standard 802.3
 MII and 7-wire 10-Mbps interface
 Station Management signaling
 On-chip CAM ( up to 21 destination addresses)
 Full-duplex mode with PAUSE feature
 Long/short packet modes
 PAD generation
1.2.12 ADC
 8-Channel Analog Input / 10-bit resolution
 500KSPS with 2.5MHz clock
1.2.13 TIMER AND WATCHDOG TIMER
 Four timers with PWM functionality, and One Watchdog timer
1.2.14 RTC
 Clock and calendar functions (BCD display)
 Leap year generator
 Alarm interrupt(ALMINT)function
 Cyclic interrupts : the interrupt cycle may be 1/256 second, 1/64 second, 1/16second,1/4second, 1/2second, or 1second
 Current Consumption : 10uA(worst condition)
 Power Supply Voltage : System power supply, Backup battery(3.0V)
1.2.15 I2C
 Two Channel
 Master mode operation only, Baud rate generation for serial clock
1.2.16 SPI
 Four channel
1.2.17 SDIO
 Two Channel
 MultiMedia Card(MMC) System Specification compatible to version 4.2
 Secure Digital Card(SDC) Physical Layer Specification compatible to version 2.0
 SDIO Specification compatible to version 2.0
 Supports SDC 1/4-bit mode, and MMC 1/4/8-bit mode
 Host clock rate programmable
 1/2/4 byte programmable transfer
 SDIO interrupts in 1-bit and 4-bit modes
 Suspend and resume operations
 Cyclic redundancy check CRC-7 for command and CRC-16 for data integrity CRC checking
 Transmit / Receive FIFO
 Supports FIFO overrun / under run prevention
 Supports GDMA transfer
1.2.18 UART
 Four Channel
 4-wire high speed Asynchronous serial interface with IrDA functionality
1.2.19 GPIO
 93 GPIOs
1.2.20 INTERRUPT
 Programmable interrupt source (16 External Interrupt, 26 Internal Interrupt)
1.2.21 CAN CONTROLLER
 PCA82C200 mode (Basic CAN mode is default)
 Extended receive buffer (64-byte FIFO)
 CAN 2.0B protocol compatibility (extended frame passive in PCA82C200 compatibility mode)
 Supports 11-bit identifier as well as 29-bit identifier
 Bit rates up to 1 Mbits/s
 PeliCAN mode extensions:
 Programmable CAN output driver configuration
 mode extensions:
 Programmable CAN output driver configuration